Direct Digital Sensing Potentiostat targeting Body-Dust

In this paper, an innovative Direct Digital Sensing Potentiostat integrated circuit for enzymeless blood glucose sensing and direct digitization is proposed to address the requirements of Body Dust. The circuit occupies a silicon area of 460 μm2 in 180nm CMOS and operates down to 0.4V power supply voltage with 4.7nW power consumption. The functionality of the proposed circuit and its performance under typical conditions and under process and temperature variations is tested by post-layout simulations

Relaxation Digital-to-Analog Converter with Radix-based Digital Correction

A Relaxation Digital-to-Analog Converter (ReDACs) with a novel, all-digital, radix-based digital correction technique for clock-indifferent linear operation is presented in this paper. The ReDAC architecture proposed in this paper does not require dedicated circuit for frequency tuning, and achieves linearity by digitally pre-processing the DAC input code by a Radix-based Digital Correction (RBDC) algorithm. The effectiveness of the proposed RBDC approach is demonstrated by transistor level simulations on a 10-bit, 1.7MS/s ReDAC in 180nm CMOS. Thanks to the proposed RBDC, under a 16% deviation from the ideal clock period, the maximum INL of the ReDAC is improved from 79.4 to 1.01LSB, its maximum DNL is improved from 158.3 to 0.45LSB and its SNDR is increased from 22.2 (3.4 ENOB) to 58.5dB (9.4 ENOB), at the cost of an increased power consumption from 1.85μW to 9.15μW

FPGA-Based Relaxation D/A Converters With Parasitics-Induced Error Suppression and Digital Self-Calibration

In this paper, the implementation on a Field Programmable Gate Array (FPGA) of Relaxation Digital to Analog Converters (ReDACs), which take advantage of the impulse response of a first-order RC network to generate and combine binary weighted voltages, is addressed. For this purpose, the dominant ReDAC nonlinearity limitation related to the parasitics of the RC network is analyzed and a simple and robust technique for its effective suppression is proposed. Moreover, a ReDAC foreground digital calibration strategy suitable to FPGA implementation is introduced to tune the clock frequency of the converter, as requested for ReDAC operation. The novel error suppression technique and calibration strategy are finally implemented on a 13-bit, 514,S/s prototype (ReDAC1) and on a 11-bit, 10.5,kS/s prototype (ReDAC2), which are experimentally characterized under static and dynamic conditions. Measured results on ReDAC1 (ReDAC2) reveal 1.68,LSB (1.53,LSB) maximum INL, 1.54,LSB (1.0,LSB) maximum DNL, 76.4,dB (67.9,dB) THD, 79.7,dB (71.4,dB) SFDR and 71.3,dB (63.3,dB) SNDR, corresponding to 11.6 (10.2) effective bits (ENOB)

Design of Relaxation Digital-to-Analog Converters for Internet of Things Applications in 40nm CMOS

A 10-bit-400kS/s and a 10-bit-2MS/s Relaxation Digital to Analog Converters (ReDAC) in 40nm are presented in this paper. The two ReDACs operate from a 600mV power supply, occupy a silicon area of less than 1,000um^2. The first/second DAC achieve a maximum INL of 0.33/0.72 LSB and a maximum DNL of 0.2/1.27 LSB and 9.9/9.4 ENOB based on post-layout simulations. The average energy per conversion is less than 1.1/0.73pJ, corresponding to a FOM of 1.1/1.08 fJ/(conv. step), which make them well suited to Internet of Things (IoT) applications. (PDF) Design of Relaxation Digital-to-Analog Converters for Internet of Things Applications in 40nm CMOS. Available from: https://www.researchgate.net/publication/336552301_Design_of_Relaxation_Digital-to-Analog_Converters_for_Internet_of_Things_Applications_in_40nm_CMOS [accessed Nov 16 2019]

Emerging Relaxation and DDPM D/A Converters: Overview and Perspectives

In this paper, two emerging, digital-intensive, matching-indifferent, bitstream digital-to-analog (D/A) conversion techniques proposed in the last years, namely: the Relaxation D/A Conversion (ReDAC) and the Dyadic Digital Pulse Modulation (DDPM)-based D/A conversion, are reviewed and compared. After the basic concepts are introduced, the main challenges and research achievements over the last years are summarized and the performance of different integrated circuit (IC), field-programmable gate array (FPGA) and microcontroller-based ReDACs and DDPM-DACs are discussed and compared, highlighting advantages and open research questions. Present applications of the two techniques in voltage and current mode A/D conversion, RF modulation, digitally controlled switching-mode power converters, and machine learning accelerators will be discussed, and future application perspectives will be outlined

Re-thinking Analog Integrated Circuits in Digital Terms: A New Design Concept for the IoT Era

A steady trend towards the design of mostly-digital and digital-friendly analog circuits, suitable to integration in mainstream nanoscale CMOS by a highly automated design flow, has been observed in the last years to address the requirements of the emerging Internet of Things (IoT) applications. In this context, this tutorial brief presents an overview of concepts and design methodologies that emerged in the last decade, aimed to the implementation of analog circuits like Operational Transconductance Amplifiers, Voltage References and Data Converters by digital circuits. The current design challenges and application scenarios as well as the future perspectives and opportunities in the field of digital-based analog processing are finally discussed

Design of an Analog and of a Digital-Based OTA in Flexible Integrated Circuit Technology

In this paper, an Analog and a Digital-Based Operational Transconductance Amplifier (OTA) in a 800nm Indium-Gallium-Zinc-Oxide (IGZO) Thin-Film Transistors (TFT) Flexible Integrated Circuits (FlexICs) technology are presented and compared on the basis of post-layout simulations.The analog OTA (A-OTA) and the Digital-Based OTA (DBOTA) occupy a total area of 42,624μm2 and 25,207μm2, respectively and - based on post-layout Monte Carlo (MC) simulations on 100 samples operated at 3.3V with 50pF capacitive load - they achieve an average gain-bandwidth product (GBW) of 58 kHz and 86 kHz, respectively, with an average power consumption of 90 μW and 113 μW. The simulated standard deviation of the input offset voltage is 22.3mV for the A-OTA and 7.2mV for the DB-OTA while the input-referred integrated noise over the entire GBW is 8.8 μVRMS and 87 μVRMS for the A-OTA and DB-OTA respectively